Raspberry Pi Pico 2

Pico 2 & RP2350 Announcement

In August 8, 2024, Raspberry Pi officially announced and launched the Pico 2 for $5 alongside the RP2350 chip. The board doubled memory, boosted clock speeds, added hardware security, and made history by including both Arm and open-source RISC-V cores on the same chip.

RP2350 Chip

Following their work on the RP1 I/O controller (used in the Raspberry Pi 5), Raspberry Pi's chip design team began engineering the RP2350. Their goal was to add robust hardware security, higher clock speeds, more RAM, and explore open-source RISC-V architectures.

Third-party hardware makers (Adafruit, SparkFun, Pimoroni) launched custom RP2350 boards. Raspberry Pi also hosted a $10,000 security hacking challenge to rigorously test the RP2350's hardware boot security, followed by the rollout of wireless versions (Pico 2 W).

Major Technical Innovations

The RP2350 features four total cores on the die—two Arm Cortex-M33 cores and two open-source Hazard3 RISC-V cores. Developers can choose which CPU architecture to run at boot time or switch between them dynamically in code.

Unlike the original Pico, the Pico 2 introduced Arm TrustZone, OTP (One-Time Programmable) memory for storing keys, signed boot support, and hardware SHA-256 acceleration—aiming squarely at commercial IoT products.

A redesigned internal switch-mode power supply lowered idle power consumption compared to the original RP2040 despite running faster cores.

Dual ARM and RISC-V architecture

At the heart of the RP2350’s dual-architecture design is a clever hardware arrangement: four physical cores on silicon exposed to the system as two logical processor sockets (Proc0 and Proc1).

Rather than switching instructions dynamically on the fly, the RP2350 treats Arm and RISC-V as hardware personalities selected at boot. The bootrom configures internal multiplexers to route the chosen cores to the central bus fabric—giving developers the flexibility to run pure Arm, pure RISC-V, or a hybrid configuration.

While it is fully feasible to run one Arm core alongside one RISC-V core in parallel, all four cores cannot run simultaneously because only two logical sockets connect to the system bus. In hybrid mode, Core 0 (Arm) and Core 1 (RISC-V) share the exact same 520 KB SRAM, Flash memory, and peripheral buses.

Software Environment

Standard MicroPython and default Pico SDK projects are pre-configured to build for uniform mode (2× ARM or 2× RISC-V) for simplicity. Running a mixed setup typically requires advanced RTOS frameworks (like Zephyr RTOS) or custom C/C++ build scripts.